Transceiver and clock generation module

ABSTRACT

A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

This application claims the benefit of U.S. provisional application Ser.No. 62/618,657, filed Jan. 18, 2018, the disclosure of which isincorporated by reference herein in its entirety.

TECHNICAL FIELD

The disclosure relates in general to a transceiver and a clockgeneration module, and more particularly to a transceiver and a clockgeneration module capable of adaptively calibrating phases of signals.

BACKGROUND

Data strobe encoding is an encoding scheme used in digital circuits, forexample, double data rate (hereinafter, DDR) synchronous dynamic randomaccess memory (hereinafter, SDRAM), for transmitting/receiving data. Thedata strobe encoding involves two signals, that is, a data signal (DQ)and a strobe signal (DQS). In short, the strobe signal (DQS) is utilizedto synchronize the data signal (DQ) under the circumstance that a phasedifference between the strobe signal (DQS) and the data signal (DQ) ismaintained.

Both the data signal (DQ) and the strobe signal (DQS) are clock-basedsignals, and different phases of the data strobe encoding rely onmulti-phase memory-clock signals. In a conventional transceiverarchitecture, a phase-locked loop (hereinafter, PLL) clock generator forgenerating multi-phase memory-clock signals is the source of allnecessary phase clocks. As wiring lengths of the phase signals providedto the data/strobe reception/transmission path are different, theaccuracy of the phase relationships cannot be guaranteed. Moreover, in areal operation environment, the process, voltage, and temperature(hereinafter, PVT) variation may cause the changes of the multi-phasememory-clock signals.

In other words, the relationships between phases of the data signal (DQ)and the strobe signal (DQS) may distort, and this may degradeperformance and data accuracy.

SUMMARY

The disclosure is directed to a transmitter and a clock generationmodule. The transmitter includes a transmitter, a receiver, and theclock generation module. With the clock generation module, phases ofsignals related to the transmitter and the receiver can be freely andinstantaneously adjusted.

According to one embodiment, a transceiver is provided. The transceiverincludes a receiver and a clock generation module. The receiver receivesa receiving-input-data (DQrd) and a receiving-input-strobe (DQSrd),wherein the receiving-input-data (DQrd) and the receiving-input-strobe(DQSrd) have a receiving-input phase difference (θrdDiff). The receiverincludes a data-receiving circuit and a strobe-receiving circuit. Thedata-receiving circuit delays the receiving-input-data (DQrd) andaccordingly generates a receiving-delayed-data (DQrd_dly). Thestrobe-receiving circuit delays the receiving-input-strobe andaccordingly generates a receiving-delayed-strobe (DQSrd_dly). The clockgeneration module is electrically connected to the receiver. The clockgeneration module includes a calibration circuit and aphase-compensation module. The calibration circuit selectively generatesone of a first set of phase control signals including astrobe-phase-compensation signal (SDQScmp) and a second set of phasecontrol signals including a data-phase-compensation signal (SDQcmp). Thephase-compensation module includes a data-phase-compensation circuit, astrobe-phase-compensation circuit, and a multi-phase signal generator.The data-phase-compensation circuit is electrically connected to thedata-receiving circuit and the calibration circuit. Thedata-phase-compensation circuit generates a receiving-path-data (DQrx)by delaying the receiving-delayed-data (DQrd_dly) with a receiving-datacompensation (θDQcmp) when the data-phase-compensation signal (SDQcmp)is generated. The strobe-phase-compensation circuit is electricallyconnected to the strobe-receiving circuit and the calibration circuit.The strobe-phase-compensation circuit generates a receiving-path-strobe(DQSrx) by delaying the receiving-delayed-strobe (DQSrd_dly) with areceiving-strobe compensation (θDQScmp) when thestrobe-phase-compensation signal (SDQScmp) is generated. Thereceiving-path-data (DQrx) and the receiving-path-strobe (DQSrx) have areceiving-path phase difference (θrxDiff) which is different from thereceiving-input phase difference (θrdDiff). The multi-phase signalgenerator is electrically connected to the calibration circuit. Themulti-phase signal generator generates a first shifted system-clocksignal (sCKp1) and a second shifted system-clock signal (sCKp2) based ona system-clock signal (sCKin). A first shifted system-clock differencebetween the second shifted system-clock signal (sCKp2) and the firstshifted system-clock signal (sCKp1) is equivalent to the receiving-pathphase difference (θrxDiff).

According to another embodiment, a clock generation module is provided.The clock generation module is electrically connected to a receiver,wherein the receiver receives a receiving-input-data (DQ_(rd)) and areceiving-input-strobe (DQS_(rd)). The receiving-input-data (DQ_(rd))and the receiving-input-strobe (DQS_(rd)) have a receiving-input phasedifference (θ_(rdDiff)). The receiving-input-data (DQ_(rd)) is delayedto generate a receiving-delayed-data (DQS_(rd_dly)), and thereceiving-input-strobe (DQS_(rd)) is delayed to generate areceiving-delayed-strobe (DQS_(rd_dly)). The clock generation moduleincludes a calibration circuit, a phase-compensation module, and amulti-phase signal generator. The calibration circuit selectivelygenerates one of a first set of phase control signals including astrobe-phase-compensation signal (S_(DQScmp)) and a second set of phasecontrol signals including a data-phase-compensation signal (S_(DQcmp)).The phase-compensation module includes a data-phase-compensation circuitand a strobe-phase-compensation circuit. The data-phase-compensationcircuit is electrically connected to the receiver. Thedata-phase-compensation circuit generates a receiving-path-data(DQ_(rx)) by delaying the receiving-delayed-data (DQ_(rd_dly)) with areceiving-data compensation (θ_(DQcmp)) when the data-phase-compensationsignal (S_(DQcmp)) is generated. The strobe-phase-compensation circuitis electrically connected to the strobe-receiving circuit and thecalibration circuit. The strobe-phase-compensation circuit generates areceiving-path-strobe (DQS_(rx)) by delaying thereceiving-delayed-strobe (DQS_(rd_dly)) with a receiving-strobecompensation (θ_(DQScmp)) when the strobe-phase-compensation signal(S_(DQScmp)) is generated. The receiving-path-data (DQ_(rx)) and thereceiving-path-strobe (DQS_(rx)) have a receiving-path phase difference(θ_(rxDiff)) which is different from the receiving-input phasedifference (θ_(rdDiff)). The multi-phase signal generator iselectrically connected to the calibration circuit. The multi-phasesignal generator generates a first shifted system-clock signal (sCKp1)and a second shifted system-clock signal (sCKp2) based on a system-clocksignal (sCKin). A first shifted system-clock difference between thesecond shifted system-clock signal (sCKp2) and the first shiftedsystem-clock signal (sCKp1) is equivalent to the receiving-path phasedifference (θ_(rxDiff)).

According to still another embodiment, a transceiver is provided. Thetransceiver includes a receiver and a clock generation module. Thereceiver receives a receiving-input-data (DQ_(rd)) and areceiving-input-strobe (DQS_(rd)), wherein the receiving-input-data(DQ_(rd)) and the receiving-input-strobe (DQS_(rd)) have areceiving-input phase difference (θ_(rdDiff)). The receiver includes adata-receiving circuit and a strobe-receiving circuit. Thedata-receiving circuit delays the receiving-input-data (DQ_(rd)) andaccordingly generates a receiving-delayed-data (DQ_(rd_dly)). Thestrobe-receiving circuit delays the receiving-input-strobe andaccordingly generates a receiving-delayed-strobe (DQS_(rd_dly)). Theclock generation module is electrically connected to the receiver. Theclock generation module includes a calibration circuit and aphase-compensation module. The calibration circuit selectively generatesone of a data-phase-compensation signal (S_(DQcmp)) and astrobe-phase-compensation signal (S_(DQScmp)) based on a phasedifference between the receiving-delayed-data (DQS_(rd_dly)), and thereceiving-delayed-strobe (DQS_(rd_dly)). The phase-compensation moduleincludes a data-phase-compensation circuit and astrobe-phase-compensation circuit. The data-phase-compensation circuitis electrically connected to the data-receiving circuit and thecalibration circuit. The data-phase-compensation circuit generates areceiving-path-data (DQ_(rx)) by delaying the receiving-delayed-data(DQ_(rd_dly)) with a receiving-data compensation (θ_(DQcmp)) accordingto the data-phase-compensation signal (S_(DQcmp)). Thestrobe-phase-compensation circuit is electrically connected to thestrobe-receiving circuit and the calibration circuit. Thestrobe-phase-compensation circuit generates a receiving-path-strobe(DQS_(rx)) by delaying the receiving-delayed-strobe (DQS_(rd_dly)) witha receiving-strobe compensation (θ_(DQScmp)) according to thestrobe-phase-compensation signal (S_(DQScmp)). The receiving-path-data(DQ_(rx)) and the receiving-path-strobe (DQS_(rx)) have a receiving-pathphase difference (θ_(rxDiff)) which is different from thereceiving-input phase difference (θ_(rdDiff)).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a transceiver.

FIG. 2A is a schematic diagram illustrating the relationship between thephases of signals in the transmitter.

FIG. 2B is a schematic diagram illustrating a relationship betweenphases of signals in the receiver.

FIG. 3 is a schematic diagram illustrating a data-receiving circuit anda strobe-receiving circuit transforming the receiving-input-data DQ_(rd)and the receiving-input-strobe DQS_(rd) to the receiving-delayed-dataDQS_(rd_dly)and the receiving-delayed-strobe DQS_(rd_dly), respectively.

FIGS. 4A and 4B are schematic diagrams illustrating cases when thestrobe-receiving circuit is compensated.

FIGS. 5A and 5B are schematic diagrams illustrating cases when thedata-receiving circuit is compensated.

FIG. 6 is a schematic diagram illustrating the receiver is used togetherwith a clock generation module.

FIG. 7 is a schematic diagram illustrating the transceiver havingself-phase-adjusting function according to the embodiment of the presentdisclosure.

FIG. 8 is a schematic diagram illustrating the signals related to themulti-phase signal generator.

FIG. 9A is a block diagram illustrating components and signals in theclock generation module.

FIG. 9B is a block diagram illustrating components and signals in themulti-phase signal generator.

FIG. 10 is a waveform diagram illustrating that none of the phases alongthe data reception path and the strobe reception path is required forcompensation.

FIG. 11 is a schematic diagram illustrating the transmission path of thephase signals without compensation.

FIG. 12 is a waveform diagram illustrating the system-clock signal sCKinand the shifted system-clock signals sCKp1(0), sCKp3(90), sCKp2(180)before and after calibration operation when the phase-drift error(Δtp2-Δtp1) is less than the default sampling-phase θ_(smp_dft).

FIG. 13 is a schematic diagram illustrating the data-receiving circuitis compensated by the data-phase-compensation signal S_(DQcmp), togetherwith adjustment of the phase-generation-paths for generating shiftedsystem-clock signals sCKp2(180) and sCKp3(90).

FIG. 14 is a waveform diagram illustrating the system-clock signal sCKinand the shifted system-clock signals sCKp1(0), sCKp3(90), sCKp2(180)before and after calibration operation when the phase-drift error(Δtp2-Δtp1) is greater than the default sampling-phase θ_(smp_dft).

FIG. 15 is a schematic diagram illustrating the data-receiving circuitis compensated by the strobe-phase-compensation signal S_(DQScmp),together with adjustment of the phase-generation-paths for generatingshifted system-clock signals sCKp1(0) and sCKp3(90).

FIG. 16 is a schematic diagram illustrating an exemplary implementationof the transceiver according to the embodiment of the presentdisclosure.

In the following detailed description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the disclosed embodiments. It will be apparent,however, that one or more embodiments may be practiced without thesespecific details. In other instances, well-known structures and devicesare schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

As mentioned above, phases control is an essential issue in memoryaccess or other devices using the strobe signal. A transceiver capableof adaptively calibrating phases of the strobe signal and the datasignal is provided. The transceiver can be an interface circuit usedtogether with a memory controller or different types of functioncircuit.

FIG. 1 is a schematic diagram illustrating a transceiver utilizing abidirectional strobe signal to access a memory. The transceiver 10includes a transmitter 101 for a memory write operation and a receiver103 for memory read operation. The transmitter 101 transmits write datato the memory 11, and the receiver 103 receives read data from memory11. The transmitter 101 and the memory 11 use a bi-directional bus toexchange memory data signal DQm and memory strobe signal DQSm.

The transmitter 101 includes a data transmission path 1011, a dataoutput buffer 1015, a strobe transmission path 1013, and a strobe outputbuffer 1017. The signal transmission flow of the memory write operationis briefly illustrated. After receiving the transmission data TX_dataand the multi-phase memory-clock signals mCKmp, the data transmissionpath 1011 generates the transmitting-output-data DQ_(wr). Then, thetransmitting-output-data DQ_(wr) are transmitted to the data outputbuffer 1015. On the other hand, the strobe transmission path 1013receives the multi-phase memory-clock signals mCKmp and generates thetransmitting-output-strobe DQS_(wr). Then, thetransmitting-output-strobe DQS_(wr) is transmitted to the strobe outputbuffer 1017. Afterwards, the transmitting-output-data DQ_(wr) and thetransmitting-output-strobe DQS_(wr) are transmitted to thebi-directional bus and considered as the memory data signal DQm and thememory strobe signal DQSm, respectively.

The receiver 103 incudes a de-serializer 1039, a data reception path1031, a data input buffer 1035, a strobe reception path 1033, and astrobe input buffer 1037. The signal transmission flow of the memoryread operation is briefly illustrated. The memory data signal DQm andthe memory strobe signal DQSm are received from the bi-directional bus.The memory data signal DQm is utilized as the receiving-input-dataDQ_(rd) (data signal driven by memory 11), and the memory strobe signalDQSm is utilized as the receiving-input-strobe DQS_(rd) (strobe signaldriven by memory 11). The data reception path 1013 receives thereceiving-input-data DQ_(rd) from the data input buffer 1035 andgenerates the receiving-path-data DQ_(rx) to the de-serializer 1039. Thestrobe reception path 1033 receives the receiving-input-strobe DQS_(rd)from the strobe input buffer 1037 and generates thereceiving-path-strobe DQS_(rx) to the de-serializer 1039. Then, thede-serializer 1039 generates the reception data RX_data.

Waveforms of the data signals and strobe signals related to theoperation of the transceiver are shown in FIGS. 2A and 2B. For the sakeof illustration, differences between the waveforms may be referred to asphase differences or time differences in the specification.

In general, double data rate memory provides a source-synchronous designthat the data signal is captured twice per clock cycle. Thus, operationsof the transceiver 10 involve two types of clock signals, that is, amemory-clock signal mCK and a system-clock signal sCKin. The frequencyof the memory-clock signal mCK is equivalent to half of the frequency ofthe system-clock signal sCKin. If the cycle of the memory-clock signalmCK is represented as Tm, and the cycle of the system-clock signal sCKinis represented as Ts, the cycle of the memory-clock signal mCK (Tm) isequivalent to twice of the cycle of the system-clock signal sCKin (Ts).That is, Tm=2*Ts. The waveforms shown in FIGS. 2A and 2B are based onthe cycle of the memory-clock signal mCK.

FIG. 2A is a schematic diagram illustrating the relationship between thephases of signals in the transmitter. In FIG. 2A, thetransmitting-output-strobe DQS_(wr) is center-aligned relative to thetransmitting-output-data DQ_(wr). That is, transitions of thetransmitting-output-strobe DQS_(wr) occur nominally 90 degrees (relativeto the mCK) out of phase with transitions of transmitting-output-dataDQ_(wr). Thus, the transmitting-output-strobe DQS_(wr) can be useddirectly to capture the transmitting-output-data DQ_(wr). As illustratedin FIG. 1, generation of the transmitting-output-data DQ_(wr) and thetransmitting-output-strobe DQS_(wr) is based on the transmission dataTX_data and the multi-phase memory-clock signals mCKmp. Thus, the basicpremise that transmitting-output-data DQ_(wr) and thetransmitting-output-strobe DQS_(wr) can be accurately generated is thatphase differences between the multi-phase memory-clock signals mCKmpmust be accurate.

FIG. 2B is a schematic diagram illustrating a relationship betweenphases of signals in the receiver. For memory read operation, thereceiving-input-strobe DQS_(rd) is assumed to be edge-aligned with thereceiving-input-data DQ_(rd). That is, the receiving-input-strobeDQS_(rd) and the receiving-input-data DQ_(rd) are clocked out of thememory by the same memory-clock signal mCK. On the other hand, thereceiving-path-strobe DQS_(rx) should be center-aligned with thereceiving-path-data DQ_(rx). Thus, the receiving-path-strobe DQS_(rx)should be delayed 90 degrees out of phase of the receiving-path-dataDQ_(rx).

Alternatively speaking, the phase difference between the phase of thereceiving-input-strobe DQS_(rd) and phase of the receiving-input-dataDQ_(rd) (for example, edge-aligned) is different from the phasedifference between the phase of the receiving-path-data (DQ_(rx)) andphase of the receiving-path-strobe (DQS_(rx)) (for example,center-aligned). In this context, the phase difference between the phaseof the receiving-input-strobe DQS_(rd) and phase of thereceiving-input-data DQ_(rd) is defined as a receiving-input phasedifference (θ_(rdDiff)), and the phase difference between the phase ofthe receiving-path-data (DQ_(rx)) and phase of the receiving-path-strobe(DQS_(rx)) is defined as a receiving-path phase difference θ_(rxDiff).The receiving-input phase difference (θ_(rxDiff)) and the receiving-pathphase difference (θ_(rxDiff)) are different.

In FIG. 2B, the difference between the rising edge ofreceiving-input-strobe DQS_(rd) and the rising edge ofreceiving-path-strobe DQS_(rx) is represented as a strobe-receivingdelay T_(DQSrx) (θ_(DQSrx)), and the difference between the rising edgeof receiving-input-data DQ_(rd) and the rising edge ofreceiving-path-data DQ_(rx) is represented as a data-receiving delayT_(DQrx) (θ_(DQrx)). Moreover, the difference between the rising edge ofreceiving-path-data DQ_(rx), and the rising edge ofreceiving-path-strobe DQS_(rx) is defined as a receiving-path phasedifference T_(rxDiff) (θ_(rxDiff)). In an ideal case, the receiving-pathphase difference T_(rxDiff) (θ_(rxDiff)) should be equivalent to ¼*Tm(that is, 90 degrees phase difference of the memory-clock signal mCK)because the receiving-path-strobe DQS_(rx) is assumed to becenter-aligned with the receiving-path-data DQ_(rx).

In this context, the 90 degrees phase difference is defined as a defaultsampling-phase θ_(smp_dft) being designed for the strobe to sample thedata. The default sampling-phase θ_(smp_dft) is equivalent to a quarterof memory-clock ¼*Tm or half of system period ½*Ts.

For the sake of illustration, the relationship between thestrobe-receiving delay T_(DQSrx) (θ_(DQSrx)), the data-receiving delayT_(DQrx) (θ_(DQrx)), and the receiving-path phase difference θ_(rxDiff)are re-drawn as horizontal bar graphs at the bottom of FIG. 2B. In thiscontext, the grid screentone represents the strobe-receiving delayθ_(DQSrx), the vertical screentone represents the data-receiving delayθ_(DQrx), and the horizontal screentone represents the defaultsampling-phase θ_(smp_dft). The length and the densities of screentoneof the horizontal bars shown in FIG. 2B represent the ideal values ofthese phases.

Usually, the data reception path 1031 has a data-receiving circuit forcontrolling phase shift of the receiving-input-data DQ_(rd), and thestrobe-receiving circuit 1032 b has a strobe-receiving circuit forcontrolling phase shift of the receiving-input-strobe DQS_(rd). However,in a case that the data reception path 1031 includes only thedata-receiving circuit and the strobe reception path 1033 includes onlythe strobe-receiving circuit, the phase difference between signalsdirectly outputted by the data-receiving circuit and thestrobe-receiving circuit may not be equivalent to the defaultsampling-phase θ_(smp_dft). In other words, the signals directlyoutputted by the data-receiving circuit and the strobe-receiving circuitare not appropriate for the de-serializer 1039.

FIG. 3 is a schematic diagram illustrating a data-receiving circuit anda strobe-receiving circuit transforming the receiving-input-data DQ_(rd)and the receiving-input-strobe DQS_(rd) to the receiving-delayed-dataDQ_(rd_dly) and the receiving-delayed-strobe DQS_(rd_dly), respectively.The data-receiving circuit 1032 a generates a receiving-delayed-dataDQ_(rd_dly) based on the receiving-input-data DQ_(rd). Thestrobe-receiving circuit 1032 b generates a receiving-delayed-strobeDQS_(rd_dly) based on the receiving-input-strobe DQS_(rd). The phasedifference between the receiving-delayed-data DQ_(rd_dly) and thereceiving-delayed-strobe DQS_(rd_dly) is defined as a receiving-circuitphase difference θ_(rcDiff_dly).

In short, because of the PVT variation, the data-receiving circuit 1032a and the strobe-receiving circuit 1032 b may not match to the expecteddesign specification. In consequence, receiving-circuit phase differenceθ_(rcDiff_dly) is not equivalent to the default sampling-phaseθ_(smp_dft). Alternatively speaking, the receiving-delayed-dataDQ_(rd_dly) and the receiving-delayed-strobe DQS_(rd_dly) cannot bedirectly used as the phase of the receiving-path-data (DQ_(rx)) and thereceiving-path-strobe (DQS_(rx)), respectively. Some variantrelationships between the phases shown in FIG. 2B are discussed in FIGS.4A, 4B, 5A, and 5B.

FIGS. 4A, 4B, 5A, and 5B illustrate various combinations of phase delayscaused by the data-receiving circuit 1032 a and the strobe-receivingcircuit 1032 b. In the following, the horizontal bars having a similartype of screentone but with different densities represent the same typeof phases but having non-ideal values. For example, a horizontal barhaving denser grid screen tone implies the strobe-receiving delayθ_(DQSrx_dly) is non-ideal, and so forth. In addition to the gridscreentone, the vertical screentone, and the horizontal screentone, thedotted screentone is further used in FIGS. 4A, 4B, 5A, and 5B torepresent a compensation phase. The compensation phase can be areceiving-strobe compensation θ_(DQScmp) related to the strobe-receivingcircuit 1032 b or a receiving-data compensation θ_(DQcmp) related to thedata-receiving circuit 1032 a.

FIGS. 4A and 4B are schematic diagrams illustrating conditions when thestrobe-receiving circuit is compensated.

In FIG. 4A, the strobe-receiving delay θ_(DQSrx_dly) is assumed to beequivalent to a predefined delay of strobe-receiving circuit 1032 b(θ_(DQSrx_idl)) (θ_(DQSrx_dly)=θ_(DQSrx_idl)), and the data-receivingdelayθ_(DQrx_dly) is assumed to be greater than a predefined delay ofdata-receiving circuit 1032 a (θ_(DQrx_idl))(θ_(DQrx_dly)>θ_(DQrx_idl)). The phase difference between the actualdelay caused by the data-receiving circuit 1032 a (that is,data-receiving delay θ_(DQrx_dly)) and the predefined delay of thedata-receiving circuit 1032 a (θ_(DQrx_idl)) is defined as phasemismatch of data-receiving circuit 1032 a(θ_(dms)=θ_(DQrx_dly)−θ_(DQrx_idl)). Because the data-receiving delayθ_(DQSrx_dly) is greater than the predefined delay of data-receivingcircuit 1032 a (θ_(DQrx_idl)) (θ_(DQrx_dly)>θ_(DQrx_idl)), thereceiving-circuit phase difference θ_(rcDiff_dly) becomes less than thedefault sampling-phase θ_(smp_dft).

In order to ensure the receiving-path phase difference θ_(rxDiff) isequivalent to the default sampling-phase θ_(smp_dft), an extra delayneeds to be inserted to the strobe reception path 1033. The extra delaybeing inserted to the strobe reception path 1033 is defined as areceiving-strobe compensation θ_(DQScmp). The receiving-strobecompensation θ_(DQScmp) is designed to be equivalent to the phasemismatch of data-receiving circuit 1032 a (θ_(dms)).

By additionally providing the receiving-strobe compensation θ_(DQScmp)to the strobe reception path 1033, a summarized strobe delayθ_(DQSrx_Ttl) representing phase delay along the strobe reception path1033 can be obtained by summing the receiving-strobe compensationθ_(DQScmp) and the strobe-receiving delay θ_(DQSrx_dly), that is,θ_(DQSrx_Ttl)=(θ_(DQScmp)+θ_(DQSrx_dly)). Thus, the difference betweenthe summarized strobe delay θ_(DQSrx_Ttl) and the data-receiving delayθ_(DQSrx_dly) is equivalent to the default sampling-phase θ_(smp_dft).

In FIG. 4B, the strobe-receiving delay θ_(DQSrx_dly) is assumed to beless than the predefined delay of strobe-receiving circuit θ_(DQSrx_idl)(θ_(DQSrx_dly)<θ_(DQSrx_idl)), and the data-receiving delay θ_(DQrx_dly)is assumed to be equivalent to the predefined delay of data-receivingcircuit θ_(DQrx_idl) (θ_(DQrx_dly)=θ_(DQrx_idl)). The phase differencebetween the actual delay caused by the strobe-receiving circuit 1032 b(that is, strobe-receiving delay θ_(DQSrx_dly)) and the predefined delayof strobe-receiving circuit 1032 b (θ_(DQSrx_idl)) is defined as phasemismatch of strobe-receiving circuit 1032 b(θ_(sms)=θ_(DQSrx_idl)−θ_(DQSrx_dly)). Because the strobe-receivingdelay θ_(DQSrx_dly) is less than the predefined delay ofstrobe-receiving circuit 1032 b (θ_(DQSrx_idl))(θ_(DQSrx_dly)<θ_(DQSrx_idl)), the receiving-path phase differenceθ_(rxDiff) becomes less than the default sampling-phase θ_(smp_dft).

Like FIG. 4A, the receiving-strobe compensation θ_(DQScmp) should beinserted to the strobe reception path 1033. In FIG. 4B, thereceiving-strobe compensation (θ_(DQScmp)) is designed to be equivalentto the phase mismatch of strobe-receiving circuit 1032 b (θ_(sms)), sothat difference between the summarized strobe delay θ_(DQSrx_Ttl) andthe data-receiving delay θ_(DQrx_dly) is equivalent to the defaultsampling-phase θ_(smp_dft).

Although the scenarios of FIGS. 4A and 4B are different, the common partof FIGS. 4A and 4B is that the receiving-circuit phase differenceθ_(rcDiff_dly) is less than the default sampling-phase θ_(smp_dft), andthe receiving-strobe compensation θ_(DQScmp) is inserted to the strobereception path 1033. As the summarized strobe delay θ_(DQSrx_Ttl)represents phase delay along the strobe reception path 1033, thedifference between the summarized strobe delay θ_(DQSrx_Ttl) and thedata-receiving delay θ_(DQrx_dly) is equivalent to the receiving-pathphase difference (θ_(rxDiff)). By inserting the receiving-strobecompensation θ_(DQScmp), the summarized strobe delay θ_(DQSrx_Ttl) isincreased, and the receiving-path phase difference θ_(rxDiff) becomesequivalent to the default sampling-phase θ_(smp_dft).

FIGS. 5A and 5B are schematic diagrams illustrating conditions when thedata-receiving circuit is compensated.

In FIG. 5A, the strobe-receiving delay θ_(DQSrx_dly) is assumed to beequivalent to the predefined delay of strobe-receiving circuitθ_(DQSrx_idl) (θ_(DQSrx_dly)=θ_(DQSrx_idl)), and the data-receivingdelay θ_(DQrx_dly) is assumed to be less than the predefined delay ofdata-receiving circuit 1032 a (θ_(DQrx_idl))(θ_(DQrx_dly)<θ_(DQrx_idl)). Because the data-receiving delayθ_(DQrx_dly) is less than the predefined delay of data-receiving circuit1032 a (θ_(DQrx_idl)) (θ_(DQrx_dly)<θ_(DQrx_idl)), the receiving-circuitphase difference θ_(rcDiff_dly) becomes greater than the defaultsampling-phase θ_(smp_dft).

In order to ensure the receiving-path phase difference θ_(rxDiff) isequivalent to the default sampling-phase θ_(smp_dft), an extra delayneeds to be inserted to the data reception path 1031. The extra delaybeing inserted to the strobe reception path 1033 is defined as areceiving-data compensation θ_(DQcmp). The receiving-data compensationθ_(DQcmp) is designed to be equivalent to the phase mismatch ofdata-receiving circuit 1032 a (θ_(dms)).

By additionally providing the receiving-data compensation θ_(DQcmp), asummarized data delay θ_(DQrx_Ttl) representing phase delay along thedata reception path 1031 can be obtained by summing the receiving-datacompensation θ_(DQcmp) and the data-receiving delay θ_(DQrx_dly), thatis, θ_(DQrx_Ttl)=(θ_(DQcmp)+θ_(DQrx_dly)). Thus, the difference betweenthe strobe-receiving delay θ_(DQSrx_dly) and the summarized data delayθ_(DQsrx_Ttl) is equivalent to the default sampling-phase θ_(smp_dft).

In FIG. 5B, the strobe-receiving delay θ_(DQSrx_dly) is assumed to begreater than the predefined delay of strobe-receiving circuitθ_(DQSrx_idl) (θ_(DQSrx_dly)>θ_(DQSrx_idl)), and the data-receivingdelay θ_(DQrx_dly) is assumed to be equivalent to the predefined delayof data-receiving circuit θ_(DQrx_idl) (θ_(DQrx_dly)=θ_(DQrx_idl)).Because the strobe-receiving delay θ_(DQSrx_dly) is greater than thepredefined delay of strobe-receiving circuit 1032 b (θ_(DQSrx_idl))(θ_(DQSrx_dly)>θ_(DQSrx_idl)), the receiving-path phase differenceθ_(rxDiff) becomes greater than the default sampling-phase θ_(smp_dft).

Like FIG. 5A, the receiving-data compensation θDQScmp should be insertedinto the data reception path. In FIG. 5B, the receiving-datacompensation θDQcmp is designed to be equivalent to the phase mismatchof strobe-receiving circuit 1032 (θsms), so that difference between thestrobe-receiving delay θDQrx_dly and the summarized data delay θDQrx_Ttlis equivalent to the default sampling-phase θsmp_dft.

Although the scenarios of FIGS. 5A and 5B are different, the common partof FIGS. 5A and 5B is that the receiving-circuit phase differenceθ_(rcDiff_dly) is greater than the default sampling-phase θ_(smp_dft),and the receiving-data compensation θ_(DQcmp) is inserted to the datareception path 1031. As the summarized data delay θ_(DQrx_Ttl)represents phase delay along the data reception path 1031, thedifference between the strobe-receiving delay θ_(DQSrx_dly) and thesummarized strobe delay θ_(DQSrx_Ttl) is equivalent to thereceiving-path phase difference (θ_(rxDiff)). By inserting thereceiving-data compensation θ_(DQcmp), the summarized data delayθ_(DQrx_Ttl) is increased, and the receiving-path phase differenceθ_(rxDiff) becomes to be equivalent to the default sampling-phaseθ_(smp_dft).

The examples shown in FIGS. 4A, 4B, 5A and 5B simplify the conditions byassuming either the strobe-receiving delay θ_(DQSrx_dly) is equivalentto the predefined delay of strobe-receiving circuit θ_(DQSrx_idl)(θ_(DQSrx_dly)=θ_(DQSrx_idl), in FIGS. 4A and 5A) or the data-receivingdelay θ_(DQSrx_dly) is equivalent to the predefined delay ofdata-receiving circuit θ_(DQrx_idl) (θ_(DQrx_dly)=θ_(DQrx_idl), in FIGS.4B and 5B). In practical application, any of the strobe-receiving delayθ_(DQSrx_dly) and the data-receiving delay θ_(DQSrx_dly) may be greaterthan/equivalent to/less than their corresponding predefined values.

When the receiving-circuit phase difference θ_(rcDiff_dly) is less thanthe default sampling-phase θ_(smp-dft), the receiving-strobecompensation θ_(DQScmp) is inserted to the strobe reception path toincrease the receiving-path phase difference θ_(rxDiff). When thereceiving-circuit phase difference θ_(rcDiff_dly) is greater than thedefault sampling-phase θ_(smp_dft), the receiving-data compensationθ_(DQcmp) is inserted to the data reception path to decrease thereceiving-path phase difference θ_(rxDiff).

According to the embodiment of the present disclosure, aphase-compensation circuit for providing the receiving-strobecompensation θ_(DQScmp) can be used in the strobe reception path 1033,and another phase-compensation circuit for providing the receiving-datacompensation θ_(DQcmp) can be used in the data reception path 1031. Anembodiment of the receiver being used together with thephase-compensation circuits along the strobe reception path 1033 and thedata reception path 1031 is shown in FIG. 6.

FIG. 6 is a schematic diagram illustrating the receiver is used togetherwith a clock generation module. The transceiver 40 includes atransmitter 401, a receiver 403, and a clock generation module 405. Theclock generation module 405 is electrically connected to the transmitter401 and the receiver 403.

The clock generation module 405 includes a phase-compensation module4058, a phase-generation-path 4051, a divider 4053, and a calibrationcircuit 4055. The calibration circuit 4055 is electrically connected tothe phase-generation-path 4051 and the phase-compensation module 4058,and the divider 4053 is electrically connected to thephase-generation-path 4051 and the transmitter 401.

The phase-compensation module 4058 includes phase-compensation circuits4058 a, 4058 b, and the phase-compensation module 4058 can be integratedinto the receiver 403. The phase-compensation circuit 4058 a iselectrically connected to the data-receiving circuit 4032 a and thede-serializer 4035. The phase-compensation circuit 4058 b iselectrically connected to the strobe-receiving circuit 4032 b and thede-serializer 4035. According to the embodiment of the presentdisclosure, the phase-compensation circuit 4858 a is configured toprovide the receiving-data compensation θ_(DQcmp), and thephase-compensation circuit 4858 b is configured to provide thereceiving-strobe compensation θ_(DQScmp).

The calibration circuit 4055 includes a phase detector 4055 a and adelay control circuit 4055 b. The phase detector 4055 a is electricallyconnected to the data-receiving circuit 4032 a, the strobe-receivingcircuit 4032 b, and the phase-compensation circuits 4058 a, 4058 b. Thedelay control circuit 4055 b is electrically connected to the phasedetector 4055 a, the phase-compensation circuits 4058 a, 4058 b, and thephase-generation-path 4051.

The phase detector 1055 a receives the receiving-delayed-dataDQ_(rd_dly) and the receiving-delayed-strobe DQS_(rd_dly) from thedata-receiving circuit 1032 a and the strobe-receiving circuit 1032 b,respectively. The phase detector 1055 a compares phases of thereceiving-delayed-data DQ_(rd_dly) and the receiving-delayed-strobeDQS_(rd_dly) and generates a phase comparison signal Spd representingthe receiving-circuit phase difference θ_(rcDiff_dly) to the delaycontrol circuit 1055 b. As illustrated in FIGS. 4A, 4B, 5A and 5B, thereceiving-circuit phase difference θ_(rcDiff_dly) is varied with changesof the strobe-receiving delay θ_(DQSrx_dly) and the data-receiving delayθ_(DQrx_idl).

The delay control circuit 4055 b compares the receiving-circuit phasedifference θ_(rcDiff_dly) and the default sampling-phase θ_(smp_dft) anddetermines whether they are equivalent. Then, the delay control circuit4055 b selectively generates one of the strobe-phase-compensation signalS_(DQScm) and the data-phase-compensation signal S_(DQcmp).

When the receiving-circuit phase difference θ_(rcDiff_dly) is equivalentto the default sampling-phase θ_(smp_dft), the receiving-delayed-dataDQ_(rd_rly) is directly used as the receiving-path-data DQ_(rx), and thereceiving-delayed-strobe DQS_(rd_rly) is directly used as thereceiving-path-strobe DQS_(rx). Meanwhile, the delay control circuit1055 b generates none of the strobe-phase-compensation signal S_(DQScmp)and the data-phase-compensation signal S_(DQcmp).

When the receiving-circuit phase difference θ_(rcDiff_dly) is less thanthe default sampling-phase θ_(smp_dft), the relationship between thestrobe-receiving delay θ_(DQSrx_dly) and the data-receiving delayθ_(DQrx-dly) is similar to the ones described in FIGS. 4A and 4B. Thus,the delay control circuit 1055 a generates the strobe-phase-compensationsignal S_(DQScmp) to the phase-compensation circuit 4058 b. Thephase-compensation circuit 4058 b is set by thestrobe-phase-compensation signal S_(DQScmp) to provide thereceiving-strobe compensation θ_(DQScmp) to the strobe reception path.By utilizing the phase-compensation circuit 4058 b to provide thereceiving-strobe compensation θ_(DQScmp), the receiving-path phasedifference θ_(rxDiff) is greater than the receiving-circuit phasedifference θ_(rcDiff_dly), and the receiving-path phase differenceθ_(rxDiff) can be adjusted to be equivalent to the defaultsampling-phase θ_(smp_dft).

When the receiving-circuit phase difference θ_(rcDiff_dly) is greaterthan the default sampling-phase θ_(smp_dft), the relationship betweenthe strobe-receiving delay θ_(DQSrx_dly) and the data-receiving delayθ_(DQrx_dly) is similar to the ones described in FIGS. 5A and 5B. Thus,the delay control circuit 1055 a generates the data-phase-compensationsignal S_(DQcmp) to the phase-compensation circuit 4058 a. Thephase-compensation circuit 4058 a is set by the data-phase-compensationsignal S_(DQcmp) to provide the receiving-data compensation θ_(DQcmp) tothe data reception path. By utilizing the phase-compensation circuit4058 a to provide the receiving-data compensation θ_(DQcmp), thereceiving-path phase difference θ_(rxDiff) can be adjusted to beequivalent to the default sampling-phase θ_(smp_dft).

With the calibration circuit 4055 and phase-compensation circuits 4058a, 4058 b, the receiver 403 is capable of maintaining the receiving-pathphase difference θ_(rxDiff) as the default sampling-phase θ_(smp_dft).

As for the phases of the transmitter 401, the phase-generation-path 4051and the divider 4053 are provided to generate the multi-phasememory-clock signals mCKmp. The phase-generation-path 4051 includes acontrollable phase-delay circuit 4051 a and a semi-sampling-delaymatching circuit 4051 b. The semi-sampling-delay matching circuit 4051 bprovides a semi-default sampling-phase being equivalent to half of thedefault sampling-phase θ_(smp_dft) (that is, ½*θ_(smp_dft)).

According to the embodiment of the present disclosure, the delay controlcircuit 1055 b transmits a phase-configuration signal S_(pcfg) to thecontrollable phase-delay circuit 4051 a. Generation of thephase-configuration signal S_(pcfg) is related to thedata-phase-compensation signal S_(DQcmp) and thestrobe-phase-compensation signal S_(DQScmp). When thedata-phase-compensation signal S_(DQcmp) is generated, thephase-configuration signal S_(pcfg) is equivalent to half of thereceiving-data compensation θ_(DQcmp). When thestrobe-phase-compensation signal S_(DQScmp) is generated, thephase-configuration signal S_(pcfg) is equivalent to half of thereceiving-strobe compensation θ_(DQScmp).

The block diagram shown in FIG. 6 is an exemplary design of atransceiver having symbiont multiple phase generation and alignmentfunction for the transmitter 401 and the receiver 403. In thisembodiment, phase control of the transmitter 401 is dependent on thesignals in the receiver 403. Thus, the embodiment shown in FIG. 6 can beutilized when the transceiver 40 operates at the initial stage.

According to the embodiment of the present disclosure, thephase-compensation circuits 4058 a, 4058 b and the controllablephase-delay circuit are controllable delay elements (hereinafter, CDE).Implementation of the CDE is not limited. For example, the CDE can be ananalog device or a digital device (for example, digitally controlleddelay-line (hereinafter, DCDL)).

The scheme shown in FIG. 6 directly utilizes signals in the receiver forphase alignment. As for the scheme shown in FIG. 7, an independent clockgeneration module and the system-clock signal sCKin from an externalsource are provided for phase alignment. As the clock generation moduleoperates independently, the transmitter and the receiver can becalibrated simultaneously. Alternative speaking, the transceiver shownin FIG. 7 has a real time self-phase-adjusting function and can beapplied in the initial stage and the normal operation stage (on-the-flycalibration).

FIG. 7 is a schematic diagram illustrating the transceiver havingself-phase-adjusting function according to the embodiment of the presentdisclosure. The transceiver 20 includes a transmitter 201, a receiver203, and a clock generation module 205. The receiver 203 includes a datainput buffer 2035, a strobe input buffer 2037, a data-receiving circuit2032 a, a strobe-receiving circuit 2032 b, and a de-serializer 2039.

The clock generation module 205 includes a multi-phase signal generator2051, a divider 2053, and a calibration circuit 2055. The multi-phasesignal generator 2051 receives a system-clock signal sCKin and generatesshifted system-clock signals sCKp1(0), sCKp2(180), sCKp3(90)accordingly. There is a 90-degree-difference (equivalent to ¼*Ts)between the shifted system-clock signals sCKp1(0), sCKp3(90), and thereis another 90-degree-difference (equivalent to ¼*Ts) between the shiftedsystem-clock signals sCKp3(90), sCKp3(180). In this context, the phasedifferences between the shifted system-clock signals sCKp1(0),sCKp2(180), sCKp3(90) are defined as shifted system-clock differences.

The divider 2053 receives the shifted system-clock signals sCKp1(0),sCKp3(90) from the multi-phase signal generator 2051 and generates themulti-phase memory-clock signals mCKmp accordingly. The calibrationcircuit 2055 receives the shifted system-clock signals sCKp1(0),sCKp2(180) from the multi-phase signal generator 2051 and generates thephase-configuration signal S_(pcfg). In addition, the calibrationcircuit 2055 selectively generates data-phase-compensation signalS_(DQcmp) and the strobe-phase-compensation signal S_(DQScmp), based onthe shifted system-clock difference between the shifted system-clocksignals sCKp2(180) and sCKp1(0).

Comparing with the calibration circuit 4055, the calibration circuit2055 receives its input from the multi-phase signal generator 2051, notdirectly from the data-receiving circuit 4032 a and the strobe-receivingcircuit 4032 b. According to the embodiment of the present disclosure,phase-generation-paths of the shifted system-clock signals sCKp1(0),sCKp2(180) are designed so that the receiving-path phase differenceθ_(rxDiff) is substantially equivalent to the shifted system-clockdifference between the shifted system-clock signal sCKp2(180) and theshifted system-clock signals sCKp1(0). In the specification, by keepingthe shifted system-clock difference between the shifted system-clocksignal sCKp2(180) and the shifted system-clock signal sCKp1(0) to beequivalent to the default sampling-phase θ_(smp_dft), the receiving-pathphase difference θ_(rxDiff) can be kept to be equivalent to the defaultsampling-phase θ_(smp_dft). Relationships between the signals shown inFIG. 7 are shown and illustrated in FIG. 8.

FIG. 8 is a schematic diagram illustrating the signals related to themulti-phase signal generator. FIG. 8 includes an upper part representingsignals generated by the multi-phase signal generator 2051, a middlepart representing the multi-phase memory-clock signals mCKmp, and alower part representing the receiving-path-data DQ_(rx) and thereceiving-path-strobe DQS_(rx).

In the upper part of FIG. 8, the waveforms Wc1, Wc2, Wc3, Wc4respectively represent the system-clock signals sCKin, and the shiftedsystem-clock signals sCKp1(0), sCKp3(90), sCKp2(180). The shiftedsystem-clock signals sCKp1(0), sCKp3(90) represent clock signals usedfor signal synchronization in the transmitter 201. In an ideal case, theshifted system-clock differences between the shifted system-clocksignals sCKp1(0), sCKp2(180), sCKp3(90) should have the followingrelationships.

Firstly, the shifted system-clock difference between the shiftedsystem-clock signal sCKp2(180) and the shifted system-clock signalsCKp1(0) should be equivalent to 180 degrees of the system-clock signalsCKin, which is equivalent to a half cycle of the system-clock signal(½*Ts). Secondly, the shifted system-clock difference between theshifted system-clock signal sCKp3(90) and the shifted system-clocksignal sCKp1(0) should be equivalent to 90 degrees of the system-clocksignal sCKin, which is equivalent to a quarter cycle of the system-clocksignal (¼*Ts). Moreover, the shifted system-clock difference between theshifted system-clock signal sCKp3(90) and the shifted system-clocksignal sCKp1(0) should be equivalent to the shifted system-clockdifference between the shifted system-clock signal sCKp2(180) and theshifted system-clock signals sCKp3(90).

In practical application, due to the PVT variation, these shiftedsystem-clock differences may not meet the above relationships by merelyusing the default design of the phase-generation-paths 2051 a, 2051 b,2051 c. Therefore, dynamically adjusting how the shifted system-clocksignals sCKp1(0), sCKp2(180), sCKp3(90) are generated must be performedwhenever necessary. Through the dynamic adjustment, the shiftedsystem-clock differences between the shifted system-clock signalssCKp1(0), sCKp2(180), sCKp3(90) can be guaranteed to be consistent withthe relationships described above, regardless the PVT variation.

According to the embodiment of the present disclosure, differencebetween the rising edge of the system-clock signal sCKin and the risingedge of the shifted system-clock signal sCKp1(0) is defined as a firstphase-difference of shifted system-clock Δtp1, and difference betweenrising edges of the system-clock signal sCKin and the shiftedsystem-clock signal sCKp2(180) is defined as a second phase-differenceof shifted system-clock Δtp2.

As shown in FIG. 7, the divider 2053 receives the shifted system clockssignal sCKp1(0), sCKp3(90) and generates the multi-phase memory-clocksignals mCKmp accordingly. As the shifted system-clock differencebetween the shifted system clocks signal sCKp1(0), sCKp3(90) isequivalent to ¼*Ts (that is, ⅛*Tm), the divider 2053 is capable ofgenerating the multi-phase memory-clock signals mCKmp having 8 differentphases (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°).

In the middle part of FIG. 8, the waveforms Wt1, Wt2, Wt3, Wt8 representthe multi-phase memory-clock signals mCKmp. The waveform Wt1 correspondsto the memory-clock signal having 0° of phase shift mCKp1(0), thewaveform Wt2 corresponds to the memory-clock signal having 45° of phaseshift mCKp2(45), the waveform Wt3 corresponds to the memory-clock signalhaving 90° of phase shift mCKp3(90), and the waveform Wt8 corresponds tothe memory-clock signal having 315° of phase shift mCKp8(315).

The lower part of FIG. 8 is the receiving-input-data DQ_(rd) and thereceiving-input-strobe DQS_(rd) in the receiver 203 in an ideal case.The waveform Wr1 represents the receiving-input-data DQ_(rd), and thewaveform Wr2 represents the receiving-input-strobe DQS_(rd). The risingedge of the waveform Wr2 is aligned to the center of thereceiving-input-data DQ_(rd).

The clock generation module 205 receives the system-clock signal sCKinfrom a clock source. The clock source can be, for example, a PLLcircuit. More details about design and control mechanism of the clockgeneration module 205 are further illustrated in FIGS. 9A and 9B.

FIG. 9A is a block diagram illustrating components and signals in theclock generation module. The multi-phase signal generator 2051 includesphase-generation-paths 2051 a, 2051 b, 2051 c. The phase-generation-path2051 a generates the shifted system-clock signal sCKp1(0), thephase-generation-path 2051 b generates the shifted system-clock signalsCKp2(180), and the phase-generation-path 2051 c generates the shiftedsystem-clock signal sCKp3(90).

The phase-generation-paths 2051 a, 2051 b are electrically connected toa clock source 30 and directly receive the system-clock signal sCKin. Onthe other hand, the phase-generation-path 2051 c is electricallyconnected to a symmetric terminal Nsym in the phase-generation-path 2051b. In other words, the phase-generation-path 2051 c receives its inputfrom a terminal inside the phase-generation-path 2051 b.

The phase-generation-path 2051 b includes symmetric sub-circuits 2061,2063, which are electrically connected to the symmetric terminal Nsym.The symmetric sub-circuits 2061, 2063 have similar internal componentsand similar features, and phase delay caused by the symmetricsub-circuit 2061 is substantially equivalent to phase delay caused bythe symmetric sub-circuit 2063. The symmetric sub-circuit 2061 receivesand delays the system-clock signal sCKin. Then, the symmetricsub-circuit 2061 transmits its output to the symmetric terminal Nsym.The symmetric sub-circuit 2063 receives its input from the symmetricterminal Nsym. Then, the symmetric sub-circuit 2063 generates theshifted system-clock signal sCKp2(180) by delaying its input.

The calibration circuit 2055 includes a phase detector 2055 a and adelay control circuit 2055 b. The phase detector 2055 a receives theshifted system-clock signal sCKp1(0) from the phase-generation-path 2051a and receives the shifted system-clock signal sCKp2(180) from thephase-generation-path 2051 b. Then, the phase detector 2055 a generatesthe phase comparison signal Spd to the delay control circuit 2055 bbased on the shifted system-clock difference between the shiftedsystem-clock signals sCKp1(0), sCKp2(180).

The delay control circuit 2055 b generates two types of phase controlsignals, that is, phase-configuration signals Scfg andphase-compensation signals Scmp. The phase-configuration signals Scfg(S_(pcfg1), S_(pcfg2a), S_(pcfg2b), S_(pcfg3)) are transmitted to themulti-phase signal generator 2051, and the phase-compensation signalsScmp (S_(DQcmp), S_(DQScmp)) are transmitted to the phase-compensationmodule 2038.

Depending relevance with the data reception path or the strobe receptionpath, these phase control signals can be classified into two sets. Thefirst set of phase control signals are the ones related to the strobereception path, that is, the phase-configuration signals S_(pcfg2a),S_(pcfg2b), and the strobe-phase-compensation signal S_(DQScmp). Thesecond set of phase control signals are the ones related to the datareception path, that is, the phase-configuration signals S_(pcfg1),S_(pcfg3), and the data-phase-compensation signal S_(DQcmp). For thesake of illustration, the first set of phase control signals(S_(pcfg2a), S_(pcfg2b), S_(DQScmp)) are shown in thick arrows, and thesecond set of phase control signals (S_(pcfg1), S_(pcfg3), S_(DQcmp))are shown in dotted thick arrows.

When the phase comparison signal Spd shows that the receiving-strobecompensation θ_(DQScmp) needs to be generated, the delay control circuit2055 b generates the first set of phase control signals (S_(pcfg2a),S_(pcfg2b), S_(DQScmp)). Among the first set of phase control signals(S_(pcfg2a), S_(pcfg2b), S_(DQScmp)), the phase-configuration signalS_(pcfg2a) is transmitted to the symmetric sub-circuit 2061, thephase-configuration signal S_(pcfg2b) is transmitted to the symmetricsub-circuit 2063, and the strobe-phase-compensation signal S_(DQScmp) istransmitted to the phase-compensation circuit 2058 b.

When the phase comparison signal Spd shows that the receiving-datacompensation θ_(DQcmp) needs to be generated, the delay control circuit2055 b generates the second set of phase control signals (S_(pcfg1),S_(pcfg3), S_(DQcmp)). Among the second set of phase control signals(S_(pcfg1), S_(pcfg3), S_(DQcmp)), the phase-configuration signalS_(pcfg1) is transmitted to the phase-generation-path 2051 a, thephase-configuration signal S_(pcfg3) is transmitted to thephase-generation-path 2051 c, and the data-phase-compensation signalS_(DQcmp) is transmitted to the phase-compensation circuit 2058 a.

FIG. 9B is a block diagram illustrating components and signals in themulti-phase signal generator. The phase-generation-path 2051 a includesa controllable phase-delay circuit 2071 being controlled by thephase-configuration signal S_(pcfg1). The phase-generation-path 2051 cincludes a controllable phase-delay circuit 2081 being controlled by thephase-configuration signal S_(pcfg3). The controllable phase-delaycircuits 2071, 2081 b are CDE circuits.

The phase-generation-path 2051 b includes the symmetric sub-circuits2061, 2063. The symmetric sub-circuit 2061 includes a controllablephase-delay circuit 2061 a and a semi-sampling-delay matching circuit2061 b. The symmetric sub-circuit 2063 includes a controllablephase-delay circuit 2063 a and semi-sampling-delay matching circuit 2063b. The controllable phase-delay circuits 2061 a, 2063 a are CDE circuitshaving identical delay settings. The controllable phase-delay circuit2061 a is controlled by the phase-configuration signal S_(pcfg2a), andthe controllable phase-delay circuit 2063 a is controlled by thephase-configuration signal S_(pcfg2b). Each of the semi-sampling-delaymatching circuit 2061 b, 2063 b provides a phase delay equivalent to onehalf of the default sampling-phase (½*θ_(smp_dft)). The phase delaysprovided by the semi-sampling-delay matching circuit 2061 b, 2063 b aredefined as a semi-default sampling-phase (½*θ_(smp_dft)), and thesemi-sampling-delay matching circuit 2061 b, 2063 b can be implementedby clock trees.

In a case that no PVT variation exists, none of the phase controlsignals are generated. For the multi-phase signal generator 2051, thephase difference between the shifted system-clock signals sCKp2(180),sCKp1(0) is subtationally equivalent to the default sampling-phaseθ_(smp_dft) because each of the semi-sampling-delay matching circuits2061 b, 2063 b provides a phase delay equivalent to one half of thedefault sampling-phase (½*θ_(smp_dft)) and the phase-generation-paths2051 a, 2051 b both receive the system-clock signal sCKin as theirinputs. As for the receiver 203, the receiving-circuit phase differenceθ_(rcDiff_dly) between the receiving-delayed-strobe DQS_(rd_dly) and thereceiving-delayed-data DQ_(rd_dly) is subtationally equivalent to thedefault sampling-phase θ_(smp_dft).

In a case that PVT variation exists, either the first set of phasecontrol signals are generated or the second set of phase control signalsare generated. Regardless the generation of the phase control signals,the phase difference between the shifted system-clock signalssCKp2(180), sCKp1(0) is no longer equivalent to the defaultsampling-phase θ_(smp_dft) if PVT variation exists, so as thereceiving-circuit phase difference θ_(rcDiff_dly).

At the same time, the PVT variation caused at the data-receiving circuit2032 a and strobe-receiving circuit 2032 b is similar to the PVTvariation caused at the semi-sampling-delay matching circuits 2061 b,2063 b. Therefore, the phase difference between the shifted system-clocksignals sCKp2(180), sCKp1(0) is substantially equivalent to thereceiving-circuit phase difference θ_(rcDiff_dly).

In the specification, the phase-generation-path 2051 a for generatingthe shifted system-clock signal sCKp1(0) can be considered as a matchingpath of the data-receiving circuit 2032 a, and the phase-generation-path2051 b for generating the shifted system-clock signal sCKp2(180) can beconsidered as a matching path of the strobe-receiving circuit 2032 b.Consequentially, under the circumstance that none of the phase controlsignals is generated, the detection result of the phase detector 2055 ais capable of representing the phase difference between the shiftedsystem-clock signals sCKp2(180), sCKp1(0), as well as the receiving-pathphase difference θ_(rxDiff).

In response to the detection result of the phase detector 2055 a, thedelay control circuit 2055 b may react differently. Firstly, thecalibration circuit 2044 may suspend generation of the phase controlsignals if the shifted system-clock difference between the shiftedsystem-clock signals sCKp1(0), sCKp2(180) is equivalent to the defaultsampling-phase θ_(smp_dft) (FIGS. 10 and 11). Secondly, the calibrationcircuit 2044 may generate the first set of phase control signals if theshifted system-clock difference between the shifted system-clock signalssCKp1(0), sCKp2(180) is less than the default sampling-phase θ_(smp_dft)(FIGS. 12 and 13). Finally, the calibration circuit 2044 may generatethe second set of phase control signals if the shifted system-clockdifference between the shifted system-clock signals sCKp1(0), sCKp2(180)is greater than the default sampling-phase θ_(smp_dft) (FIGS. 14 and15). These three cases are described respectively.

FIG. 10 is a waveform diagram illustrating that none of the phases alongthe data reception path and the strobe reception path is required forcompensation. When the phase detector 2055 a determines that the shiftedsystem-clock difference between the shifted system-clock signalssCKp1(0), sCKp2(180) is equivalent to the default sampling-phaseθ_(smp_dft), this implies that the phase mismatch of data-receivingcircuit θ_(dms) is equivalent to the phase mismatch of strobe-receivingcircuit θ_(sms). Therefore, the delay control circuit 2055 b generatesnone of the phase control signals.

FIG. 11 is a schematic diagram illustrating the transmission path of thephase signals without compensation. As none of the phase control signalsis generated, the controllable phase-delay circuits 2071, 2081, 2061 a,2063 b and the phase-compensation circuits 2058 a, 2058 b are alldisabled.

Therefore, the shifted system-clock signal sCKp1(0) is generated bydirectly using the system-clock signal sCKin, and the shiftedsystem-clock signal sCKp3(90) is generated by directly using the signalat the symmetric terminal Nsym. The signal at the symmetric terminalNsym is generated by delaying the system-clock signal sCKin with thesemi-default sampling-phase (½*θ_(smp_dft)) corresponding to thesemi-sampling-delay matching circuit 2061 b. The shifted system-clocksignal sCKp2(180) is generated by delaying the signal at the symmetricterminal Nsym with the semi-default sampling-phase (½*θ_(smp_dft))corresponding to the semi-sampling-delay matching circuit 2063 b.

In other words, the shifted system-clock signal sCKp2(180) is generatedby delaying the system-clock signal sCKin with the defaultsampling-phase θ_(smp_dft). Moreover, the shifted system-clock signalsCKp3(90) is generated by delaying the system-clock signal sCKin withthe semi-default sampling-phase (½*θ_(smp_dft)).

In practice, generation of the shifted system-clock signals sCKp1(0),sCKp2(180) and sCKp3(90) may not be identical to the ones shown in FIG.10. Consequentially, a phase-drift error (Δtp2-Δtp1) representing thedifference between the second phase-difference of shifted system-clockΔtp2 and the first phase-difference of shifted system-clock Δtp1 is notequivalent to the default sampling-phase θsmp_dft.

FIG. 12 is a waveform diagram illustrating the system-clock signal sCKinand the shifted system-clock signals sCKp1(0), sCKp3(90), sCKp2(180)before and after calibration operation when the phase-drift error(Δtp2-Δtp1) is less than the default sampling-phase θ_(smp_dft). Beforethe multi-phase signal generator 2051 is calibrated, the phase-drifterror (Δtp2-Δtp1) is less than the default sampling-phase θ_(smp_dft).In the specification, the receiving-circuit phase differenceθ_(rcDiff_dly) is subtationally equivalent to the phase-drift error(Δtp2-Δtp1) before the calibration circuit 2055 generates any of thephase control signals (θ_(rcDiff_dly)=(Δtp2-Δtp1) ). Thus, thereceiving-circuit phase difference θ_(rcDiff_dly)is less than thedefault sampling-phase θ_(smp_dft). That is,θ_(rcDiff_dly)=(Δtp2-Δtp1)<θ_(smp_dft).

Under such circumstance, the delay control circuit 2055 b generates thefirst set of phase control signals (S_(pcfg2a), S_(pcfg2b), S_(DQScmp))to the controllable phase-delay circuits 2061 a, 2063 a, and thephase-compensation circuits 2058 b. Then, phase delays along thephase-generation-paths 2051 b, and the strobe reception path is adjustedaccordingly.

For FIG. 12, the phase-drift error (Δtp2-Δtp1) is utilized to determinethe receiving-strobe compensation θ_(DQScmp), that is,θ_(DQScmp)=θ_(smp_dft)-(Δtp2-Δtp1). Therefore, the shifted system-clocksignal sCKp1(0) remains unchanged, the shifted system-clock signalssCKp2(180), sCKp3(90) and the receiving-delayed-strobe DQS_(rd_dly) areadjusted. The amounts of phase adjustment of the shifted system-clocksignals sCKp2(180) and sCKp3(90) are determined by thephase-configuration signals S_(pcfg2a), S_(pcfg2b). According to thephase-configuration signals S_(pcfg2a), S_(pcfg2b), the shiftedsystem-clock signal sCKp2(180) should be shifted by the receiving-strobecompensation θ_(DQScmp).

Consequentially, the difference between the rising edges of thesystem-clock signal sCKin and the shifted system-clock signal sCKp2(180)is increased by the receiving-strobe compensation θ_(DQScmp). Thedifference between the rising edges of the system-clock signal sCKin andthe shifted system-clock signal sCKp2(180) after being increased isdefined as an updated second phase-difference of shifted system-clockΔtp2′. Moreover, the relationship between the second phase-difference ofshifted system-clock Δtp2 and the updated second phase-difference ofshifted system-clock Δtp2′ can be represented as Δtp2′=Δtp2+θ_(DQScmp).Meanwhile, according to the phase-configuration signals S_(pcfg2a), theshifted system-clock signal sCKp3(90) should be shifted by ½*θ_(DQScmp).

After the multi-phase signal generator 2051 is calibrated, thedifference between the updated second phase-difference of shiftedsystem-clock Δtp2′ and the first phase-difference of shiftedsystem-clock Δtp1 is equivalent to the default sampling-phaseθ_(smp_dft). Thus, the receiving-path phase difference θ_(rxDiff) isequivalent to the default sampling-phase θ_(smp_dft). That is,θ_(rxDiff)=(Δtp2′-Δtp1)=θ_(smp_dft).

FIG. 13 is a schematic diagram illustrating the data-receiving circuitis compensated by the data-phase-compensation signal S_(DQcmp), togetherwith adjustment of phase-generation-paths for generating the shiftedsystem-clock signals sCKp2(180) and sCKp3(90). Please refer to FIG. 13and Table 1 together.

TABLE 1 (Δtp2 − Δtp1) < θ_(smp)_dft. phase control first set of phaseS_(pcfg2a) is transmitted to the signals generated control signalscontrollable phase-delay by the calibration circuit 2061a circuitS_(pcfg2b) is transmitted to the controllable phase-delay circuit 2063aS_(DQScmp) is transmitted to the phase-compensation circuit 2058b secondset of phase none of S_(pcfg1), S_(pcfg3), control signals S_(DQcmp) isgenerated multi-phase signal sCKp1(0) controllable phase-delay generatorcircuit 2071 is disabled. Bypass sCKin as sCKp1(0) sCKp3(90)controllable phase-delay circuit 2081 is disabled. Bypass signal at Nysmas sCKp3(90) sCKp2(180) controllable phase-delay circuits 2061a, 2063aare enabled. Shift sCKin with the delay caused by controllablephase-delay circuits 20161a, 2063a and semi-sampling-delay matchingcircuits 2061b, 2063b phase-compensation phase-compensation BypassDQ_(rd)_dly as DQ_(rx) module circuit 2058a (data) phase-compensationenabled by S_(DQScmp) circuit 2058b shift DQS_(rd)_dly with θ_(DQScmp)(strobe) to generate DQS_(rx) θ_(DQScmp) = θ_(smp)_dft − (Δtp2 − Δtp1))

When the phase comparison signal Spd represents that(Δtp2-Δtp1)<θ_(smp_dft)., the delay control circuit 2055 b generates thefirst set of phase control signals but suspends generating the secondset of phase control signals. The phase-configuration signal S_(pcfg2a)is transmitted to the controllable phase-delay circuit 2061 a, thephase-configuration signal S_(pcfg2b) is transmitted to the controllablephase-delay circuit 2063 a. and the strobe-phase-compensation signalS_(DQScmp) is transmitted to the phase-compensation circuit 2058 b.

For the phase-generation-path 2051 a, the controllable phase-delaycircuit 2071 is disabled because the phase-configuration signalS_(pcfg1) is not generated. Thus, no extra delay is caused at thephase-generation-path 2051 a. Therefore, the system-clock signal sCKinis directly used as the shifted system-clock signal sCkp1(0).

For the phase-generation-path 2051 c, the controllable phase-delaycircuit 2081 is disabled because the phase-configuration signalS_(pcfg3) is not generated. Thus, the shifted system-clock signalsCKp3(90) can be obtained by acquiring the signal at the symmetricterminal Nsym. Moreover, the signal at the symmetric terminal Nsym canbe obtained by shifting the sCKin with (½*θ_(DQScmp)+½*θ_(smp_dft)),that is, the summation of controllable delay caused by the controllablephase-delay circuit 2061 a (½*θ_(DQScmp)) and the semi-defaultsampling-phase caused by the semi-sampling-delay matching circuit 2061 b(½*θ_(smp_dft)).

For the phase-generation-path 2051 b, the controllable phase-delaycircuits 2061 a, 2063 a are enabled because the phase-configurationsignals S_(pcfg2a), S_(pcfg2b) are generated. Therefore, the shiftedsystem-clock signal sCKp2(180) can be obtained by delaying thesystem-clock signal sCKin with summation of the receiving-strobecompensation θ_(DQScmp) and the default sampling-phase(θ_(DQScmp)+θ_(smp_dft)), which can be obtained by summing thecontrollable delays caused by the controllable phase-delay circuit 2061a, 2063 a (½*θ_(DQScmp) of each) and semi-default sampling-phase causedby the semi-sampling-delay matching circuit 2061 b, 2063 b(½*θ_(smp-dft) of each).

The phase-compensation circuit 2058 b receives thestrobe-phase-compensation signal S_(DQScmp) from the delay controlcircuit 2055 b. Then, the phase-compensation circuit 2058 b shifts thereceiving-delayed-strobe DQS_(rd_dly) with the receiving-strobecompensation θ_(DQScmp) and generates the receiving-path-strobe DQS_(rx)accordingly.

FIG. 14 is a waveform diagram illustrating the system-clock signal sCKinand the shifted system-clock signals sCKp1(0), sCKp3(90), sCKp2(180)before and after calibration operation when the phase-drift error(Δtp2-Δtp1) is greater than the default sampling-phase θ_(smp_dft).Before the multi-phase signal generator 2051 is calibrated, thedifference between the second phase-difference of shifted system-clockΔtp2 and the first phase-difference of shifted system-clock Δtp1 isgreater than the default sampling-phase θ_(smp_dft). In thespecification, the receiving-circuit phase difference θ_(rcDiff_dly) issubtationally equivalent to the phase-drift error (Δtp2-Δtp1) before thecalibration circuit 2055 generates any of the phase control signals(θ_(rcDiff_dly)=(Δtp2-Δtp1)). Thus, the receiving-circuit phasedifference θ_(rcDiff_dly) is greater than the default sampling-phaseθ_(smp-dft). That is, θ_(rcDiff_dly)=(Δtp2-Δtp1)>θ_(smp-dft).

Under such circumstance, the delay control circuit 2055 b generates thesecond set of phase control signals (S_(pcfg1), S_(pcfg3), S_(DQcmp)) tothe controllable phase-delay circuits 2071, 2081, and thephase-compensation circuit 2058 a. Then, phase delays along thephase-generation-paths 2051 a, 2051 c, and the data reception path areadjusted accordingly.

For FIG. 14, the phase-drift error (Δtp2-Δtp1) is utilized to determinethe receiving-data compensation θ_(DQcmp), that is,θ_(DQcmp)=(Δtp2-Δtp1)-θ_(smp-dft) Therefore, the shifted system-clocksignal sCKp2(180) remains unchanged, the shifted system-clock signalssCKp1(0), sCKp3(90) and the receiving-delayed-data DQ_(rd_dly) areadjusted. The amounts of phase adjustment of the shifted system-clocksignals sCKp1(0) and sCKp3(90) are respectively determined by thephase-configuration signals S_(pcfg1), S_(pcfg3). According to thephase-configuration signals S_(pcfg1), the shifted system-clock signalsCKp1(0) should be shifted by the receiving-strobe compensationθ_(DQScmp).

Consequentially, the difference between the rising edges of thesystem-clock signal sCKin and the shifted system-clock signal sCKp1(0)is increased by the receiving-strobe compensation θDQScmp. Thedifference between the rising edges of the system-clock signal sCKin andthe shifted system-clock signal sCKp1(0) after being increased isdefined as an updated first phase-difference of shifted system-clockΔtp1′. Moreover, the relationship between the first phase-drift ofshifted system clock Δtp1 and the updated first phase-difference ofshifted system-clock Δtp1′ can be represented as Δtp1′=Δtp1+θDQcmp.According to the phase-configuration signals Spcfg3, the system-clocksignal sCKp3(90) should be shifted by ½*θDQScmp.

After the multi-phase signal generator 2051 is calibrated, thedifference between the second phase-difference of shifted system-clockΔtp2 and the updated first phase-difference of shifted system-clockΔtp1′ is equivalent to the default sampling-phase θ_(smp_dft). Thus, thereceiving-path phase difference θ_(rxDiff) is equivalent to the defaultsampling-phase θ_(smp_dft). That is,θ_(rxDiff)=(Δtp2-Δtp1′)=θ_(smp_dft).

FIG. 15 is a schematic diagram illustrating the data-receiving circuitis compensated by the strobe-phase-compensation signal S_(DQScmp),together with adjustment of phase-generation-paths for generating theshifted system-clock signals sCKp1(0) and sCKp3(90). Please refer toFIG. 15 and Table 2 together.

TABLE 2 (Δtp2 − Δtp1) > θ_(smp)_dft. Phase control first set of phasenone of S_(pcfg2a), S_(pcfg2b), signals generated control signalsS_(DQScmp) is generated by the calibration second set of phase S_(pcfg1)is transmitted to he circuit control signals controllable phase-delaycircuit 2071 S_(pcfg3) is transmitted to the controllable phase-delaycircuit 2081 S_(DQcmp) is transmitted to the phase-compensation circuit2058a multi-phase signal sCKp1(0) controllable phase-delay generatorcircuit 2071 is enabled by Spcfg1. delay sCKin with θ_(DQScmp) togenerate sCKp3(0) sCKp3(90) controllable phase-delay circuit 2081 isenabled by Scfg3. delay signal at Nysm with ½*θ_(DQScmp) to generatesCKp3(90) sCKp2(180) controllable phase-delay circuits 2061a, 2063a aredisabled. shift sCKin with the delay caused by semi-sampling-delaymatching circuits 2061b, 2063b to generate sCKp2(180) phase-compensationPhase-compensation enabled by S_(DQcmp) module circuit 2058a (data)shift DQ_(rd)_dly with θ_(DQcmp) to generate DQ_(rx) θ_(DQcmp) = (Δtp2 −Δtp1) − θ_(smp)_dft Phase-compensation Bypass DQS_(rd)_dly as DQS_(rx)circuit 2058b (strobe)

When the phase comparison signal Spd represents that(Δtp2-Δtp1)>θ_(smp-dft)., the delay control circuit 2055 b generates thesecond set of phase control signals but suspends generating the firstset of phase control signals. The phase-configuration signal S_(pcfg1)is transmitted to the controllable phase-delay circuit 2071, thephase-configuration signal S_(pcfg2b) is transmitted to the controllablephase-delay circuit 2081. and the data-phase-compensation signalS_(DQcmp) is transmitted to the phase-compensation circuit 2058 a.

For the phase-generation-path 2051 a, the controllable phase-delaycircuit 2071 is enabled because the phase-configuration signal S_(pcfg1)is generated. Thus, extra delay is caused at the phase-generation-path2051 a. Therefore, the shifted system-clock signal sCkp1(0) can begenerated by delaying the system-clock signal sCKin with θ_(DQcmp), thatis, the controllable delay caused by the controllable phase-delaycircuit 2071.

For the phase-generation-path 2051 c, the controllable phase-delaycircuit 2081 is enabled because the phase-configuration signal S_(pcfg2)is generated. As the input of the controllable phase-delay circuit 2081is conducted from the symmetric terminal Nsym, the shifted system-clocksignal sCkp3(90) can be obtained by delaying the signal at the symmetricterminal Nsym with ½*θ_(DQcmp), that is, the controllable delay causedby the controllable phase-delay circuit 2081. Furthermore, the signal atthe symmetric terminal Nsym can be obtained by delaying the system-clocksignal sCKin with (½*θ_(smp_dft)), that is, the semi-sampling-predefineddelay caused by the semi-sampling-delay matching circuit 2061 b.Therefore, the shifted system-clock signal sCkp3(90) can be obtained byshifting the system-clock signal sCKin with (½*θ_(DQcmp)+½*θ_(smp_dft)).

For the phase-generation-path 2051 b, the controllable phase-delaycircuits 2061 a, 2063 a are disabled because the phase-configurationsignals S_(pcfg2a), S_(pcfg2b) are not generated. Therefore, the shiftedsystem-clock signal sCKp2(180) can be obtained by delaying thesystem-clock signal sCKin with the receiving-circuit phase differenceθ_(rcDiff_dly), that is, the summation of semi-default sampling-phasescaused by the semi-sampling-delay matching circuits 2061 b, 2063 b(½*θ_(smp_dft)+½*θ_(smp_dft)=θ_(smp_dft)).

The phase-compensation circuit 2058 a receives thedata-phase-compensation signal S_(DQcmp) from the delay control circuit2055 b. Then, the phase-compensation circuit 2058 a shifts thereceiving-delayed-data DQ_(rd_dly) with the receiving-data compensationθ_(DQcmp) and generates the receiving-path-data DQ_(rx) accordingly.

FIG. 16 is a schematic diagram illustrating an exemplary implementationof the transceiver according to the embodiment of the presentdisclosure. The transceiver includes a transmitter 301, a cockgeneration module 305 and a receiver 303.

The transmitter 301 includes delay adjust circuits 3016 a, 3016 b,serializers 3015 a, 3015 b, data output buffers 3015, and a strobeoutput buffer 3015 b. The number of the serializers 3015 a and the dataoutput buffers 3015 are related to the number of data bits. The receiver303 includes data input buffers 3035, a strobe input buffer 3037, astrobe generator 3032 b, and a de-serializer 3039. 3058 a. The number ofthe de-serializer 3039 is related to the number of data bits.

The clock generation module 305 includes a multi-phase signal generator3051, a divider 3053, a calibration circuit 3055, and phase-compensationcircuits 3058 a, 3058 b. The multi-phase signal generator 3051 includescontrollable phase-delay circuits 3071 a, 3071 b, 3081, 3061 a, 3063 aand semi-sampling-delay matching circuits 3061 b 3063 b. Thecontrollable phase-delays circuits 3071 a, 3071 b constructs thephase-generation-path of the shifted system-clock signal sCKp1(0). Thecontrollable phase-delays circuit 3081 is electrically connected tosymmetric terminal Nsym to construct the phase-generation-path of theshifted system-clock signal sCKp3(90). The controllable phase-delayscircuit 3061 a and the semi-sampling-delay matching circuit 3061 bcollectively construct a symmetric sub-circuit 3061, and thecontrollable phase-delays circuit 3063 a and the semi-sampling-delaymatching circuit 3063 b collectively construct a symmetric sub-circuit3063. The symmetric sub-circuits 3061, 3063 jointly construct thephase-generation-path of the shifted system-clock signal sCKp2(180).

The divider 3053 receives the shifted system-clock signals sCKp1(0),sCKp3(90) to generate the multi-phase memory-clock signals mCKmp. Thecalibration circuit 3055 includes a phase detector 3055 a and a delaycontrol circuit 3055 b.

The phase-compensation circuit 3058 a is placed in the data receptionpath, and the phase-compensation circuit 3058 b is placed in the strobereception path. The strobe-phase-compensation signal S_(DQScmp) carriesDQS offset code to set the cascaded DCDL pairs in phase-compensationcircuit 3058 b. The data-phase-compensation signal S_(DQcmp) carries DQoffset code to set the DCDL pair in phase-compensation circuit 3058 b.

In practical application, the phase-compensation circuits 3058 a, 3058 bcan be considered as part of the receiver or as a part of the clockgeneration module 305. Moreover, the cascaded DCDL pairs 3059 may becontrolled by two sources. That is, the cascaded DCDL pairs 3059 mayreceive a common DQ offset code being equally applied to all thecascaded DCDL pairs 3059, and several unique DQ offset codes which areseparately applied to each of the DCDL pairs 3059. The common DQ offsetcode is determined by the data-phase-compensation signal S_(DQcmp), andthe unique DQ offset codes are respectively related to different databits.

As illustrated above, the transceiver according to the embodiment of thepresent disclosure has a self-adjusting function so that thereceiving-path phase difference (θ_(rxDiff)) between thereceiving-path-data (DQ_(rx)) and the receiving-path-strobe (DQS_(rx))is maintained in a real-time manner. With the clock generation module,the transceiver is capable of instantaneously calibrating phases ofsignals related to the transmitter and/or the receiver. Although theexamples illustrated above are based on the DDR memory, the embodimentscan be applied to single data rate synchronous DRAM (SDR) or other typesof circuits using the data strobe encoding by merely changing phasedifference settings.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the disclosed embodiments.It is intended that the specification and examples be considered asexemplary only, with a true scope of the disclosure being indicated bythe following claims and their equivalents.

What is claimed is:
 1. A transceiver, comprising: a receiver, configuredto receive a receiving-input-data and a receiving-input-strobe, whereinthe receiving-input-data and the receiving-input-strobe have areceiving-input phase difference, and the receiver comprises: adata-receiving circuit configured to delay the receiving-input-data andaccordingly generate a receiving-delayed-data; a strobe-receivingcircuit, configured to delay the receiving-input-strobe and accordinglygenerate a receiving-delayed-strobe; and a clock generation module,electrically connected to the receiver, comprising: a calibrationcircuit, configured to selectively generate one of a first set of phasecontrol signals comprising a strobe-phase-compensation signal and asecond set of phase control signals comprising a data-phase-compensationsignal; and a phase-compensation module, comprising: adata-phase-compensation circuit, electrically connected to thedata-receiving circuit and the calibration circuit, configured togenerate a receiving-path-data by delaying the receiving-delayed-datawith a receiving-data compensation when the data-phase-compensationsignal is generated; and a strobe-phase-compensation circuit,electrically connected to the strobe-receiving circuit and thecalibration circuit, configured to generate a receiving-path-strobe bydelaying the receiving-delayed-strobe with a receiving-strobecompensation when the strobe-phase-compensation signal is generated,wherein the receiving-path-data and the receiving-path-strobe have areceiving-path phase difference which is different from thereceiving-input phase difference; and a multi-phase signal generator,electrically connected to the calibration circuit, configured togenerate a first shifted system-clock signal and a second shiftedsystem-clock signal based on a system-clock signal, wherein a firstshifted system-clock difference between the second shifted system-clocksignal and the first shifted system-clock signal is equivalent to thereceiving-path phase difference.
 2. The transceiver according to claim1, wherein the receiving-input-data and the receiving-input-strobe areedge-aligned, and the receiving-path-strobe is 90 degrees out of phasewith the receiving-path-data.
 3. The transceiver according to claim 1,wherein the multi-phase signal generator further generates a thirdshifted system-clock signal, and a second shifted system-clockdifference between the third shifted system clock and the first shiftedsystem-clock signal is equivalent to a third shifted system-clockdifference between the second shifted system-clock signal and the thirdsifted system-clock signal, wherein the first shifted system-clockdifference is equivalent to a summation of the second shiftedsystem-clock difference and the third shifted system-clock difference.4. The transceiver according to claim 3, wherein the transceiver furthercomprises a transmitter and the clock generation module furthercomprises: a divider, electrically connected to the multi-phase signalgenerator and the transmitter, configured to receive the first shiftedsystem-clock signal and the third shifted system-clock signal, andaccordingly generate a plurality of multi-phase memory-clock signals. 5.The transceiver according to claim 4, wherein cycle of the system-clocksignal is equivalent to half of cycles of the plurality of multi-phasememory-clock signals.
 6. The transceiver according to claim 1, whereinthe multi-phase signal generator comprises: a firstphase-generation-path, configured to receive the system-clock signal andgenerate the first shifted system-clock signal according to a firstphase-configuration signal from the calibration circuit; a secondphase-generation-path, comprising: a first sub-circuit, electricallyconnected to a symmetric terminal and configured to receive thesystem-clock signal and selectively receive a first-secondphase-configuration signal from the calibration circuit; and a secondsub-circuit, electrically connected to the symmetric terminal,configured to selectively receive a second-second phase-configurationsignal from the calibration circuit and generate the second shiftedsystem-clock signal, wherein the first sub-circuit and the secondsub-circuit are symmetric; and a third phase-generation-path,electrically connected to the symmetric terminal, configured toselectively receive a third phase-configuration signal from thecalibration circuit and generate the third system-clock signal, whereinthe first set of phase control signals further comprises thefirst-second phase-configuration signal and the second-secondphase-configuration signal, and the second set of phase control signalsfurther comprises the first phase-configuration signal and the thirdphase-configuration signal.
 7. The transceiver according to claim 6,wherein the calibration circuit generates the first set of phase controlsignals when phase difference between the receiving-delayed-strobe, andthe receiving-delayed-data is satisfied with a first predefinedcomparison condition; and the calibration circuit generates the secondset of phase control signals when the phase difference between thereceiving-delayed-strobe, and the receiving-delayed-data is satisfiedwith a second predefined comparison condition, wherein thereceiving-delayed-data is corresponding to the first shiftedsystem-clock signal, and the receiving-delayed-strobe is correspondingto the second shifted system-clock signal.
 8. The transceiver accordingto claim 7, wherein the first predefined comparison condition issatisfied when the phase difference between the second shiftedsystem-clock signal and the first shifted system-clock signal is greaterthan a default sampling-phase; and the second predefined comparisoncondition is satisfied when the phase difference between the secondshifted system-clock signal and the first shifted system-clock signal isless than the default sampling-phase.
 9. The transceiver according toclaim 8, wherein the default sampling-phase is equivalent to half ofcycle of the system-clock signal.
 10. The transceiver according to claim6, wherein the first phase-generation-path comprises: a firstcontrollable phase-delay circuit, configured to delay the system-clocksignal with a first controllable phase-delay to generate the firstshifted system-clock signal when the first phase-configuration signal isgenerated.
 11. The transceiver according to claim 10, wherein the firstsub-circuit comprises: a second controllable phase-delay circuitcorresponding to a second controllable phase-delay; and a firstsemi-sampling-delay matching circuit corresponding to a firstsemi-default sampling-phase; and the second sub-circuit comprises: athird controllable phase-delay circuit corresponding to a thirdcontrollable phase-delay; and a second semi-sampling-delay matchingcircuit corresponding to a second semi-default sampling-phase, whereinthe second controllable phase-delay is equivalent to the thirdcontrollable phase-delay, and the first semi-default sampling-phase isequivalent to the second semi-default sampling-phase.
 12. Thetransceiver according to claim 11, wherein summation of the firstsemi-default sampling-phase and the second semi-default sampling-phaseis equivalent to half of cycle of the system-clock signal.
 13. Thetransceiver according to claim 11, wherein the first sub-circuit isconfigured to delay the system-clock signal with the second controllablephase-delay and the first semi-default sampling-phase and generate asignal at the symmetric terminal when the first-secondphase-configuration signal is generated; and the second sub-circuit isconfigured to delay the signal at the symmetric terminal with the thirdcontrollable phase-delay and the second semi-default sampling-phase togenerate the second shifted system-clock signal when the second-secondphase-configuration signal is generated.
 14. The transceiver accordingto claim 13, wherein the third phase-generation-path comprises: a fourthcontrollable phase-delay circuit, configured to delay the signal at thesymmetric terminal with a fourth controllable phase-delay to generatethe third shifted system-clock signal when the third phase-configurationsignal is generated.
 15. The transceiver according to claim 14, whereinthe third phase-generation-path utilizes the signal at the symmetricterminal as the third shifted system-clock signal when the thirdphase-configuration signal is not generated.
 16. The transceiveraccording to claim 14, wherein the first controllable phase-delaycircuit and the fourth phase delay circuit are disabled when the firstpredefined comparison condition is unsatisfied; and the secondcontrollable phase-delay circuit and the third phase delay circuit aredisabled when the second predefined comparison condition is unsatisfied.17. The transceiver according to claim 6, wherein the calibrationcircuit comprises: a phase detector, electrically connected to the firstphase-generation-path and the second phase-generation-path, configuredto receive the first shifted system-clock signal and the second shiftedsystem-clock signal and generate a phase comparison signal according tocomparison of phases of the first shifted system-clock signal and thesecond shifted system-clock signal; and a delay control circuit,electrically connected to the phase detector, configured to generate thefirst set of phase control signals and the second set of phase controlsignals according to the phase comparison signal.
 18. The transceiveraccording to claim 1, wherein the multi-phase signal generator receivesthe system-clock signal from a phase-locked loop (hereinafter, PLL)circuit.
 19. A clock generation module, electrically connected to areceiver, wherein the receiver receives a receiving-input-data and areceiving-input-strobe, wherein the receiving-input-data and thereceiving-input-strobe have a receiving-input phase difference, thereceiving-input-data is delayed to generate a receiving-delayed-data,and the receiving-input-strobe is delayed to generate areceiving-delayed-strobe, and the clock generation module comprises: acalibration circuit, configured to selectively generate one of a firstset of phase control signals comprising a strobe-phase-compensationsignal and a second set of phase control signals comprising adata-phase-compensation signal; and a phase-compensation module,comprising: a data-phase-compensation circuit, electrically connected tothe receiver, configured to generate a receiving-path-data by delayingthe receiving-delayed-data with a receiving-data compensation when thedata-phase-compensation signal is generated; and astrobe-phase-compensation circuit, electrically connected to thestrobe-receiving circuit and the calibration circuit, configured togenerate a receiving-path-strobe by delaying thereceiving-delayed-strobe with a receiving-strobe compensation when thestrobe-phase-compensation signal is generated, wherein thereceiving-path-data and the receiving-path-strobe have a receiving-pathphase difference which is different from the receiving-input phasedifference; and a multi-phase signal generator, electrically connectedto the calibration circuit, configured to generate a first shiftedsystem-clock signal and a second shifted system-clock signal based on asystem-clock signal, wherein a first shifted system-clock differencebetween the second shifted system-clock signal and the first shiftedsystem-clock signal is equivalent to the receiving-path phasedifference.